The present invention relates generally to data processing, and more particularly to a method and apparatus pertaining to data capture.
In a data processing system it is usually necessary to transfer data between system components, and this transfer is often accomplished over a data bus. Data is placed on the bus by a first component, for example a central processing unit (CPU), and received from or captured from the bus by second component, for example a memory device. One such method of data transfer is a source synchronous burst operation bus system. In such a system, there is provided a core clock synchronized to a system clock, and one or more data clocks or strobes synchronized off the core clock, to coordinate data transfers between components. As used in this patent, the term xe2x80x9cclock cyclexe2x80x9d shall mean a distinct data processing cycle such that, for instance, the clock cycle rate is equal to the data rate.
One method of data capture in a source synchronous burst operation bus system is to use the rising or falling edge of a strobe (referred to herein as xe2x80x9cSTRBxe2x80x9d) signal to sample the even number data (for example data0 and data2 . . . ), and use the rising or falling edge of the inverse strobe (referred to herein as xe2x80x9cSTRB#xe2x80x9d) signal to sample the odd number data (for example, data1, data3, . . . ), and to synchronize the data (data0, data1, data2, data3, . . . ) one-by-one to the core clock by using an address strobe (ADS)-generated pulse. In this scheme, the serial-to-parallel conversion occurs after synchronization, and each data item is extended for two clock cycles before it is latched on core clock. A clock cycle may thus correspond to one or more periods of the core clock, or it may correspond to a phase or other sub-multiple of a period. In such a method, the setup time margin and hold time margin to latch the data to the core clock is specified as:
Setup time margin=clock cyclexe2x88x92SKEWxe2x88x92STRB distribution skewxe2x88x92clock-to-out
Hold time margin=clock cyclexe2x88x92SKEWxe2x88x92STRB distribution skew+clock-to-out
where SKEW is the skew+jitter between the data strobes (STRB/STRB#) and the core clock.
In a system with a core clock cycle of 2.0 to 2.5 ns (400-500 MHZ clock), and with a SKEW of about 0.3-0.5 ns at worst case, fulfilling this setup time margin and hold time margin requirement is still achievable. This further assumes that STRB distribution skew, which varies depending on how close the STRB and STRB# pins of the circuit component are to the input buffers of the component, and how they are routed, can still be kept smaller than 0.5 clock cycle to allow data to be latched by STRB (STRB#). However, if the core clock cycle is raised, for example, to 1.6 Ghz, one clock cycle would be only 0.625 ns. In such a case, the data synchronization scheme described above will not work. Furthermore, with clock cycles as high as this, sending an ADS-generated pulse from the center of a die of a processing component to the I/O areas on one clock cycle can in itself be a challenging task.
The present invention provides method and apparatus, wherein data is serially latched into a set of latches, delayed and parallelized, and synchronized to a clock for further processing. These and further aspects of the embodiments of the invention are described and claimed below.